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SPONSORS

 

        

 

  MiNapad 2019

 

Tuesday May 21st

15h30 to 17h30 Lecture Subramanian S. lyer

(Samueli School of Engineering, University of California, Los Angeles USA) Makalu Room

Packaging- When all else fails! Or Why I became a packaging Engineer

Co-Organized with  

Wednesday May 22nd

8h45                    Welcome to MiNaPAD

9h00                    Opening by Alexandre Val (Auditorium)

9h30                    Keynote 1: Subramanian S. lyer

“A Moore’s law for packaging” (Auditorium)

 

10h15                  Exhibition Opening (Exhibition Hall)

 

Session A : MEMS & LED

Session B : Process Optimization

10h45

CMOS Image Sensor Packaging Technology (A. Attard, UTAC Group)

Copper Wire Robustness for High Volume Production

(J. Catania, ST Microelectronics)

11h10

Curved Full-Frame CMOS Sensor: Impact on Electro-Optical Performances

(B. Chambion, CEA-LETI)

Adhesion strength of Epoxy Molding Compound to metals in a semiconductor package (F. Viviani, St Microelectronics)

11h35

A New Method for a Failure Characterization of a Flip-Chip Assembly of pixelated LED Light Source Package

(S. Beddar, Versailles Saint-Quentin University)

Innovative materiel solutions for MEMs and sensor packages

(T. Inukai, Sumitomo Bakelite Europe)

 

12h00–13h15 Lunch (Exhibition Hall– Exhibition)

13h15

Keynote 2: Jacques Fournier (CEA-LETI): Secure Packaging for Addressing Hardware Security Challenges (Auditorium)

 

Session C : Interposer 2.5D/TSV/3D

Session L: Market analysis

14h30

New Copper and Cobalt wet metallization enabling multiple Integrations for FEOL and BEOL (M. Baus, AVENI)

Electronics in Europe

(G. Dubois, DECISION)

14h55

Die-to-Wafer direct bonding for production environment with a new Flip-Chip bonder (P. Metzger, SET)

Packaging for the Automotive Industry

(M. Ibrahim, YOLE Développement)

15h20

Metrology for High Density Wafer Level Fan-Out & TSV based stacking

(D. Alliata, UNITYSC)

Session M: Specific topics

Backside Protection against physical attacks for secure chips or SiP

(S. Borel, CEA LETI)

Layout Design of I/O Libraries for Wirebond & Flip-Chip Package options

(K. Chanumolu, ARM)

15h45

Advanced Packaging Material Developments for 3D Stacking and System-In –Package

(R. De Witt, Henkel Electronics Materials

16h10-16h35 Exhibition/coffee break sponsored by

 

 

Session D : Dicing/Picking 1

Session E : PCB1-Embedded

 

16h35

Plasma Dicing: A Device-Enabling Technology for advanced Packaging and 3D Integration

(P. Bezard, PLASMA-THERM)

EHDICOS “Embedded Technologies” with standards Components

(F. Lechleiter, CIMULEC)

17h00

A more than Moore Enabling Wafer Dicing Technology

(J. van Borkulo, ASMPT)

EDDEMA: Embedded Die Design Environment and Methodology for Automotive Applications

(N. Marier, VALEO)

17h25

Development of Back Griding/Mask 2 in 1 Tape for Plasma Dicing Process

(T. Uchimaya, FURUKAWA ELECTRIC)

Advanced PCB Technology for Integrated Flexible Electronics

(J. Verhegge, ACB)

 

17h50-18h30     Exhibition

19h30                  Social Event - Restaurant “Les Jardins de Sainte Cécile”

  18h30 – 19h30 Extra: Visit of Rembrandt exposition located close to Social event and sponsored by CEA LETI – Please book it due to limited to 25 persons (English language guide.

 

 

 

Thursday May 23rd

8h30                     Keynote 3: Jean-Marc Yannou (ASE): Car Electrification: a revolution also for the

semiconductor packaging marketing (Auditorium)

 

Session F : Characterization/Reliability

Session G : Advanced Process

9h30

Mechanical Behavior of SAC305 Lead free Alloy (J. Vieilledent, THALES Global Services)

Innovative Implementation of additive Manufacturing for Advanced Microelectronics Packaging

(A. Roshangias, CTR)

9h55

Thermomechanical Behavior Characterization new Development for high Resolution multi-scale Analyses

(D. Ecoiffier, INSIDIX)

Increased Integration Density of optoelectronic Modules by Through-Silicon Laser Soldering adapted for Wafer Level Packaging (S, Reiken, FICONTEC)

10h20

A comprehensive Methodology for Design for Package Miniaturization

(R. Duca, ST Microelectronics)

 

Moisture uptake of PECVD dielectrics at ambient and accelerated Test Conditions

V. Cartaillier, (Laboratory IMS & ST Microelectronics)

 

10h45-11h10     Exhibition/coffee break sponsored by

 

Session H : SiP

Session I : Joining/Advanced Process

11h10

Miniaturized Medical Devices

(P. von Meiss, VALTRONIC)

Statistical Study of SAC Solder joints in QFN and BGA assemblies

(H. Fremont, Laboratory IMS)

11h35

Evolution of RF SiP and challenges ahead

(C. Zinck, ASE)

Key Advances In Void Reduction and Warpage Mitigation in the Reflow Process (J. Balackyi, HELLER Industries)

12h00– 13h00   Lunch & Exhibition (Exhibition hall)

13h00                  Keynote 4: Harald Gall (AT&S): Microelectronics and Integration Technologies:

Enabler for Smart Mobility (Auditorium)

 

Session J : PCB2-Power

Session K : Dicing/Picking 2

13h35

High Power PCB for air plane applications (G. Belijar, IRT)

Sawing Capability Study for Front-Side Chipping Reduction (M. Tumiati, ST Microelectronics)

14h00

Double Side Interconnection for vertical power components based on Macro and Nano structured Copper Interfaces and printed Circuit Board Technologies

(B. Djuric, MITSUBISHI Electric)

Packaging of a MOEMS LIDAR Sub Assembly for distance Metering on a 3D housing

(J. Abdilla, BESI AT)

 

14h25

Thermal Management in the PCB

(S. Houivet, ELVIA)

 

 

Laser-lift-off (LLO) and CONDOx for Wafer ultra-thinning process for 3D stacked Devices, TSV, eWLB and WLCSP and DICING WITHOUT Adhesives for MEMS and optical devices (G. Klug, DISCO)

15h00-15h20     Exhibition / Coffee Break

 

15h20                  Keynote 5: Emilie Jolivet (YOLE) / Stéphane Elisabeth (SYSTEM PLUS):

System-in-Package and heterogeneous integration: evolution or revolution? (Auditorium)

16h15                  Best Paper Awards sponsored by

 

16h30                  End of MiNaPAD2019